(a) Field of the Invention
The invention relates to a switching device, particularly to a multi-phase clock switching device.
(b) Description of the Related Art
FIG. 1A shows a schematic diagram illustrating a conventional phase lock loop 10 and a phase selection device 11. The phase lock loop 10 outputs a plurality of phase clock signals. The phase selection device 11 receives these phase clock signals and selects one of phase clock signals as an output signal O according to a switching signal S.
In general, a conventional phase selection device 11 includes a plurality of phase selection circuits 11a and a plurality of logic units 11b, as shown in FIG. 1B. The circuitry layout and configuration of the phase selection circuits 11a and the logic units 11b are shown in the figure and will not be described further in details.
Generally, a chip may include functions of clock generation and switching clock. The phase selection device 11 is usually used to switch clock, if a circuit on the chip needs to adjust phase of the clock.
FIG. 1C shows waveforms of the phase selection device 11. The phase selection circuits 11a0 and 11a1 in FIG. 1B are used as an example to describe an operating method of a conventional circuit. Please refer to FIG. 1B and FIG. 1C.
As shown in FIG. 1C, the general phase selection circuits 11a0 and 11a1 includes four states:                state 1: the switching signal S switches the phase clock signal P0 to P1 (that is, the phase selection circuit 11a1 is selected) where P0 is at a high level and P1 is at a low level (preparing for changing from a low level to a high level) at the time;        state 2: the switching signal S switches the phase clock signal P0 to P1 (that is, the phase selection circuit 11a1 is selected) where P0 is at a low level and P1 is at a high level (preparing for changing from a high level to a low level) at the time;        state 3: the switching signal S switches the phase clock signal P1 to P0 (that is, the phase selection circuit 11a0 is selected) where P1 is at a low level (preparing for changing from a low level to a high level) and P0 is at a high level at the time; and        state 4: the switching signal S switches the phase clock signal P1 to P0 (that is, the phase selection circuit 11a0 is selected) where P1 is at a high level (preparing for changing from a high level to a low level) and P0 is at a low level at the time.        
It should be noted that in FIG. 1C, the clock drawn by the thicker lines represents that the clock signal is effective, that is, the clock signal is a part signal of the output signal O and the clock drawn by the thinner lines represents that the clock signal is not effective, that is, the clock signal has no contribution to the output signal O.
Further the output signal O of the conventional phase selection device 11 is a continuous signal contributed by the effective clock signals in states 1-4. However, the output signal O of the phase selection device 11 discontinues between t0˜t1 because the output signal O at t0 is at a low level and the output signal O at t1 is at a high level under the state 2. This phenomenon is called “glitch” and such a phenomenon causes the fault of a circuit using this clock.